A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2 RRAM Binary/Compute-in-Memory Macro with 4.23× Improvement in Density and >75% Use of Sensing Dynamic Range

📋 论文概要

该论文提出了一种基于RRAM的二进制存内计算宏，在40nm工艺下实现了64kb容量、26.56TOPS/W能效和2.37Mb/mm2密度，相比之前工作密度提升4.23倍且利用率超过75%，有效解决了RRAM存内计算在面积受限集成电路中的实用性问题。

💡 主要创新点

• 通过电路和架构优化大幅提升RRAM存内计算宏的面积密度，实现4.23倍密度改进。
• 采用二进制计算方案并保持高利用率（>75%），在有限面积内获得高能效和计算能力。
• 在40nm工艺下展示了RRAM存内计算宏的实际芯片实现，验证了面积效率的重要性。

🏷 关键词

📄 原文摘要

Compute-in-Memory (CIM) using emerging nonvolatile (eNVM) memory technologies, such as resistive random-access memory (RRAM), has been shown by several implemented macros to be an energy-efficient alternative to traditional von Neumann architectures [1-6]. Since moving data on- and off-chip has a high energy cost, area efficiency is important to the practical utility of CIM with RRAM. Many systems demonstrated so far have not reported area efficiency or addressed the challenges CIM with RRAM presents with respect to practical area-constrained integrated circuits. Figure 16.2.1 shows the topology of the implemented RRAM macro and presents three challenges. (1) As suggested above, peripheral area overhead for eNVM-based CIM

👥 作者与机构

Samuel D. Spetalnick1, Muya Chang1, Brian Crafton1, Win-San Khwa2,

Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute of Technology, Atlanta, GA TSMC Corporate Research, Hsinchu, Taiwan 3 TSMC Design Technology, Hsinchu, Taiwan 1