⚡ 本页包含 AI 生成的分析内容，仅供参考
本文实现了一款1Tb容量、4b/单元（QLC）、4平面、162层堆叠的3D NAND闪存芯片，并集成了2.4Gb/s的高速I/O接口，旨在提升存储密度和数据传输速率。
Pradeep Anantula1, Stanley Jeong1, Anirudh Amarnath1, Siddhesh Darne1, Sneha Bhatia2, Tianyu Tang1, Aditya Arya1, Naman Rastogi1, Naoki Ookuma1, Hiroyuki Mizukoshi1, Alex Yap1, Demin Wang1, Steve Kim1, Yonggang Wu1, Min Peng1, Jason Lu1, Tommy Ip1, Seema Malhotra1, David Han1, Masatoshi Okumura1, Jiwen Liu1, John Sohn1, Hardwell Chibvongodze1, Muralikrishna Balaga1, Aki Matsuda1, Chakshu Puri1, Chen Chen1, Indra K V1, Chaitanya G1, Venky Ramachandra1, Yosuke Kato1, Ravi Kumar1, Huijuan Wang1, Farookh Moogat1, In-Soo Yoon1, Kazushige Kanda2, Takahiro Shimizu2, Noboru Shibata2, Takashi Shigeoka2, Kosuke Yanagidaira2, Takuyo Kodama2, Ryo Fukuda2, Yasuhiro Hirashima2, Mitsuhiro Abe2 Western Digital, Milpitas, CA KIOXIA, Tokyo, Japan 1 2 The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2, which is 8.7% higher than prior work [1]. High-performance is the key
Jong Yuh1, Jason Li1, Heguang Li1, Yoshihiro Oyama1, Cynthia Hsu1,