A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup

📋 论文概要

该论文提出了一种基于电压插值器的分数-N类型I采样锁相环（PLL），工作在2-2.48GHz频段，采用22nm FinFET工艺。它解决了传统数字PLL中量化噪声和杂散问题，同时辅助快速晶体启动，实现低抖动、小面积和低功耗，适用于物联网应用。

💡 主要创新点

• 采用电压插值器实现分数-N频率合成，避免数字域量化噪声，简化校准复杂度。
• 类型I采样架构与快速晶体启动技术结合，降低抖动和功耗的同时加快系统启动时间。

🏷 关键词

📄 原文摘要

Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser Kurd, Mohamed Abdel-moneum, Brent Carlton Intel, Hillsboro, OR A high-performance clock generator with extremely low jitter, area, and power consumption is the key building block in the emerging Internet of Things (IoT) to connect billions of devices. Recently, digital phase-locked loops (DPLL) [1,2] have been developed to eliminate the bulky loop filter (LF) in type-II charge-pump PLLs. However, they suffer from quantization noise and spurs, requiring complex calibration techniques. Therefore, type-I reference-sampling PLLs are gaining popularity [3,4] to achieve wider bandwidths in smaller areas. A passive sampling phase detector (SPD) has a much lower noise contribution than a charge pump. But, a fractional-N implementation requires a digital-to-time converter (DTC) to align the input clocks of the SPD for spur mitigation

👥 作者与机构

Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban,