A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-LogicBased ADC-less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

📋 论文概要

本文提出了一种基于动态逻辑的无ADC SRAM存内计算宏，在28nm工艺下实现了1.041 Mb/mm²的高密度和27.38 TOPS/W的高能效，支持有符号INT8向量-矩阵乘法。该设计通过去除传统ADC和静态逻辑，显著减少了计算电路面积，适用于深度神经网络推理等高效能嵌入式系统。

💡 主要创新点

• 采用动态逻辑替代传统的ADC或静态逻辑来实现存内计算，大幅降低宏单元面积。
• 实现了高密度（1.041 Mb/mm²）和高能效（27.38 TOPS/W）的SRAM CIM宏，支持有符号INT8运算。
• 具备可重构性，适用于多种向量处理应用。

🏷 关键词

📄 原文摘要

China 4 Duke University, Durham, NC 1 2 Advanced intelligent embedded systems perform cognitive tasks with highly-efficient vector-processing units for deep neural network (DNN) inference and other vector-based signal processing using limited power. SRAM-based compute-in-memory (CIM) achieves high energy efficiency for vector-matrix multiplications, offers <1ns read/write speed, and saves vastly repeating memory accesses. However, prior SRAM CIM macros require a large area for compute circuits (either using ADC for analog CIM [1-4] or CMOS static logic for all-digital CIM [5-6]), have limited CIM functions, and use fixed vectorprocessing dimensions that cause a low-spatial-utilization rate when deploying DNN (Fig.

👥 作者与机构

Bonan Yan1, Jeng-Long Hsu2, Pang-Cheng Yu2, Chia-Chi Lee2, Yaojun Zhang3,

Wenshuo Yue1, Guoqiang Mei3, Yuchao Yang1, Yue Yang2, Hai Li4, Yiran Chen4, Ru Huang1 Peking University, Beijing, China NeoNexus, Singapore, Singapore 3 Pimchip Technology, Beijing,