A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array

📋 论文概要

本文实现了一款1Tb容量、4b/cell的3D-NAND闪存，采用176层技术和CMOS-under-the-Array架构，通过4独立平面读取提高并行性，位密度达到14.7Gb/mm2。

💡 主要创新点

• 采用176层堆叠和4b/cell技术实现1Tb高密度存储，位密度达14.7Gb/mm2。
• 引入4独立平面读取架构，支持多平面并行操作，提升读性能。
• 利用CMOS-under-the-Array设计优化面积效率。

🏷 关键词

📄 原文摘要

Jonathan Pabustan1, Joe Xu1, Srinivas Deshmukh1, Kim-Fung Chan1, Michael Piccardi1, Kevin Xu1, Guan Wang1, Kaveh Shakeri1, Vipul Patel1, Tomoko Iwasaki1, Tongji Wang1, Padma Musunuri1, Carl Gu1, Ali Mohammadzadeh1, Ali Ghalam1, Violante Moschiano2, Tommaso Vali2, Jaekwan Park1, June Lee1, Ramin Ghodsi1 Micron Technology, San Jose, CA Micron Technology, Avezzano, Italy 1 2 This paper presents a 1Tb 4b/cell 3D-NAND-Flash memory on a 176-tier technology with a 14.7Gb/mm2 bit density. The die is organized using a 4-plane architecture for multiplane operations with a 16KB page size. The 1×4 plane architecture improves both program and read throughput, without increasing the die size. Periphery circuitry and page buffers are placed under the array using 5th-generation CMOS under array (CuA) technology. To improve random read performance, a faster read is provided with a read concurrency feature: allowing four independent multiplane page read addresses. The

👥 作者与机构

Ted Pekny1, Luyen Vu1, Jeff Tsai1, Dheeraj Srinivasan1, Erwin Yu1,