A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS

📋 论文概要

本文提出了一种电容驱动的片上链路，通过结合前馈均衡（FFE）和地强制偏置技术，在5.6mm的DRAM全局总线长度上实现了12.0Gb/s/线的数据速率和78.8fJ/b/mm的能效。该设计解决了传统中继器驱动片上互连的功耗和面积限制，提高了DRAM接口的带宽效率。

💡 主要创新点

• 采用电容驱动取代传统中继器，显著降低片上长互连的功耗和延迟。
• 提出FFE结合地强制偏置技术，补偿信道损耗并抑制串扰，实现高速传输。

🏷 关键词

📄 原文摘要

Advances in virtual reality, artificial intelligence, and big data have increased demand for high-bandwidth memory. Accordingly, pre-fetch sizes have also increased with DRAM generations, meaning an increased number of global bus lines. An increase to this number is limited as it also increases the chip size; instead, the data-rate per lane can be increased for higher throughput [1]. As the global bus lines are on-chip wires in a DRAM chip, they can be driven capacitively. Prior work [2,3] has shown the superior efficiency of capacitive drivers, over conventional repeaters, in driving on-chip wires at the cost of a reduced voltage swing. However, as there is no well-defined DC level on the capacitively-driven wires [4], wire biasing is fraught with implementation challenges [3]. To define the DC potential on the interconnect, prior work sent signals differentially [2,4,5] or dissipated static power to define the DC level [3]. Unfortunately, these

👥 作者与机构

Sangyoon Lee, Jaekwang Yun, Suhwan Kim

Seoul National University, Seoul, Korea