⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种用于HBM接口的TIA端接双码收发器，通过边缘延迟均衡、ECC和失配校准技术，在10 Gb/s速率下实现了0.385 pJ/bit的能效，解决了高带宽内存接口中功耗与数据速率之间的矛盾。
Hyunsu Park1, Yoonjae Choi1, Jincheol Sim1, Jonghyuck Choi1, Youngwook Kwon1, Junyoung Song2, Chulwoo Kim1 Korea University, Seoul, Korea Incheon National University, Incheon, Korea 1 2 The bandwidth of parallel DRAM I/O has increased to meet big-data requirements. High bandwidth memory (HBM) interfaces use up to 1024 pins, and with an increased clock frequency, their power consumption has also increased [1]. Figure 28.5.1 shows four HBM interface approaches. Conventional HBM interfaces use a termination-less structure at the receiver to reduce power consumption. For higher data rates receiver-side termination can be used to improve signal integrity. However, this causes a large static current for long consecutive identical digits (CID). Di-code signaling can be used in HBM interfaces to reduce this static current. Nevertheless, there are still design constraints for conventional di-code interfaces, such as equalization, offset voltage, and series
with Edge-Delayed Equalization, ECC, and Mismatch, Calibration for HBM Interfaces