⚡ 本页包含 AI 生成的分析内容，仅供参考
论文介绍了一款1Tb容量、3bit/单元的第八代3D NAND闪存，实现了164MB/s的写入吞吐量和2.4Gb/s的接口速度，以满足数据量指数增长对更高密度和更快速度的需求。
Yeong Seon Kim, Daehoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyunjun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Jisang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myunghoon Choi, Wontae Kim, Jungsoo Kim, Seokmin Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-Yub Lee, Jaihyuk Song Samsung Electronics, Hwaseong, Korea As data sizes increase exponentially, the demand for higher-density NAND with a smaller cell size and a higher interface speed has also increased [1-4]. However, the increased number of WL-stack layers results in a smaller sensing circuit size and a smaller WL-toWL spacing, which increases the intrinsic transistor variation and the inter-cell interference. One way to achieve good density while maintaining system performance is to support more multiple-plane operations with a circuit under cell array architecture,
Moosung Kim, Sung Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee,