A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter

📋 论文概要

针对LPDDR5移动DRAM中电源噪声引起的时钟抖动问题，提出了一种带二阶自适应补偿的时钟分配网络，在低功耗下有效抑制了抖动。

💡 主要创新点

• 提出二阶自适应抖动消除电路，实时补偿电源噪声引起的时钟抖动。
• 时钟分配网络集成自适应机制，无需传统电压调节器，降低了功耗和面积。

🏷 关键词

📄 原文摘要

SK hynix, Icheon, Korea 3 Korea Aerospace Research Institute, Daejeon, Korea 4 KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a speed of 6.4Gb/s has recently been announced [1]. One of the most critical issues of high-performance DRAM is the supply-noise induced jitter (SIJ) generated by the clock distribution network (CDN) and the transmit and receive paths. Conventional CDN SIJ coping methods use supply voltage regulators and decoupling capacitors. Unfortunately, a supply regulator is not suitable for low-voltage mobile DRAM due to the required dropout voltage headroom, while the decoupling capacitor cannot sufficiently filter low-frequency noise without requiring excessive area. In this paper, we propose an SIJ cancelation technique based on an adaptive filter (AF) using a least mean square (LMS) algorithm; it cancels jitter along the CDN and the transmit and receive paths, which

👥 作者与机构

Yeonwook Jung*1, Seongseop Lee*2, Hyojun Kim3, SeongHwan Cho4

Samsung Electronics, Hwaseong-si, Korea