ISSCC 2020
Session 25
Digital Circuits
A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regula
ISSCC 2012
Session 13
Memory
Capacitive-Coupling Wordline Boosting with SelfInduced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM
embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the