Capacitive-Coupling Wordline Boosting with SelfInduced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM

📋 论文概要

本文提出了一种电容耦合字线升压与自感应VCC塌陷技术，用于降低22nm 8T SRAM的写操作最小电压（VMIN），解决了工艺变化导致的写操作困难问题。通过该技术，有效提升了SRAM在宽电压范围内的写可靠性。

💡 主要创新点

• 采用电容耦合方式实现字线升压，增强写驱动能力而不增加额外功耗。
• 利用自感应VCC塌陷机制，动态降低写操作期间存储单元的供电电压，进一步降低写VMIN。

🏷 关键词

📄 原文摘要

embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the need for SRAM arrays that can achieve both high performance and low minimum voltage of operation (VMIN). The 8T bitcell (Fig. 13.3.1) is commonly used in these applications because its decoupled read and write ports offer fast read (RD) and write (WR) operations with generally lower VMIN than the 6T bitcell. However, process variations result in mismatches between the pull-up and access devices limiting write VMIN, and/or between read port and keeper transistors limiting read VMIN. Traditional device up-sizing provides diminishing returns at a large area and power cost [2].

👥 作者与机构

Jaydeep Kulkarni, Bibiche Geuskens, Tanay Karnik,

Muhammad Khellah, James Tschanz, Vivek De Intel, Hillsboro, OR High-performance microprocessors and SoCs include multiple