ISSCC 2018
Session 22
Data Converters
A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at Nyquist in 14nm CMOS FinFET
Alessandro Cevrero1, Ilter Ozkaya1,3, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland; 3EPFL, Lausanne, Switzerland 1 2 Optical communication standards, such as ITU
ISSCC 2017
Session 28
Data Converters
A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
Alessandro Cevrero1, Ilter Ozkaya1, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland 1 2 High-speed SAR ADCs became popular with modern CMOS technologies because of t