机构

Qualcomm

3 篇 ISSCC 论文

ISSCC 2026 Session 10 Digital Circuits
A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction
Yimai Peng1, Daniel Yingling1, Basma Hajri2, Robert Vachon1, Fikre Gebreyohannes2, Vincent Li3, Ghanshyam Chhetri4, Keit
Abstract A 2nm clock-edge architecture (CEA) for an NPU matrix-multiplication unit (MXU) features dual-edge-triggered (DET) flip-flops, DET clock-gating circuits, and an adaptive clock dutycycle controller to achieve iso
Qualcomm, Raleigh, NC, 2Qualcomm, Cork, Ireland, 3Qualcomm, San Diego,
ISSCC 2021 Session 35 Digital Circuits
Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm HexagonTM Processor
Vijay Kiran Kalyanam1, Eric Mahurin1, Keith Bowman2, Suresh Venkumahanti1
Qualcomm, Raleigh, NC 1 2 The Hexagon™ compute DSP (CDSP) integrates a master VLIW scalar processor and a slave vector coprocessor to enable high-performance and energy-efficient computing for multimedia, voice, audio, v
Qualcomm, Austin, TX
ISSCC 2010 Session 15 Digital Processors
A 45nm CMOS 13-Port 64-Word 41b Fully Associative Content-Addressable Register File
Greg Burda, Yesh Kolla, Jim Dieffenderfer, Fadi Hamdan
The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the techn
Qualcomm, Raleigh, NC