ISSCC 2012
Session 8
Data Converters
A 72dB-DR ΔΣ CT Modulator Using Digitally Estimated Auxiliary DAC Linearization Achieving 88fJ/conv in a 25MHz BW
modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3rd or 4th-order loop-filters [1,2]. In order to improve power efficiency, circuit and a
ISSCC 2011
Session 27
Data Converters
An 8mW 50MS/s CT ΔΣ Modulator with 81dB SFDR and Digital Background DAC Linearization
There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) – especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design