A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

📋 论文概要

本文提出一种改进锁存器的时钟再生比较器，在65nm CMOS工艺下实现高速低功耗性能。在1.2V供电时，比较器工作频率达7GHz且功耗仅1.3mW；在0.6V供电时，工作频率为700MHz且功耗47µW。解决了高速比较器在高电压下功耗大、低电压下速度慢的矛盾。

💡 主要创新点

• 通过修改锁存器结构，优化正反馈路径，使得比较器在宽电压范围内保持高速性能。
• 实现了在1.2V和0.6V两种供电电压下的可重构工作模式，适应不同功耗和速度需求。

🏷 关键词

📄 原文摘要

Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications. In [1] a 10GHz 3-stage comparator in 1.2V 0.11µm CMOS is presented and is designed to extract every 4th bit of a 40Gb/s data stream. A BER<10−12 for 1Vpp at the input is achieved. Depending of the intended application, the constant tail current and the low-voltage swing of the CML blocks may or may not be beneficial. In [2] a latch-type sense amplifier (in 1.5V 0.13µm CMOS) for use in SRAMs is investigated. The delay time is 119ps for an input voltage difference of 100mV. A disadvantage is that for proper operation a sufficiently large supply voltage is needed due to the stack of transistors and therefore the comparison time is longer than 11ns at 0.7V. In [3] a comparator with similar circuit structure in 1.8V 0.18µm CMOS is described, consuming 350µW at 1.4GHz. The standard

👥 作者与机构

Bernhard Goll, Horst Zimmermann

Vienna University of Technology, Vienna, Austria