⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种在32nm SOI FinFET工艺中实现的亚1V带隙电压基准电路，解决了传统二极管和电阻在薄SOI层中无法实现的问题。通过采用新型电路结构，成功在FinFET技术中实现了低电压带隙基准。
likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value. The conventional CMOS bandgap voltage reference adds a proportional-toabsolute-temperature (PTAT) voltage and a complementary-to-absolute-temperature (CTAT) vol
A.J. Annema1, P. Veldhorst1, G. Doornbos2, B. Nauta1, 1
University of Twente, Enschede, Netherlands NXP-TSMC Research Center, Leuven, Belgium 2 The bulk CMOS technology is expected to scale down to about 32nm node and