A 2mm2 0.1-to-5GHz SDR Receiver in 45nm Digital CMOS

📋 论文概要

该论文提出了一款在45nm数字CMOS工艺中实现的0.1至5GHz软件定义无线电接收机，芯片面积仅为2mm²。通过采用可重构的射频前端和数字辅助校准技术，解决了多标准无线通信中宽带、低功耗和低成本集成的挑战。

💡 主要创新点

• 采用可重构的射频前端架构，支持0.1至5GHz的宽频段覆盖，适应多种无线标准。
• 利用45nm数字CMOS工艺实现高集成度，芯片面积仅2mm²，显著降低成本和功耗。
• 引入数字辅助校准技术，补偿工艺偏差和失配，提升接收机性能。

🏷 关键词

📄 原文摘要

Kameswaran Vengattaramane1,2, Michiel Steyaert2, Julien Ryckaert1, Michael Goffioul1, Björn Debaillie1, Joris Van Driessche1, Jan Craninckx1, Mark Ingels1 1 IMEC, Leuven, Belgium, 2KULeuven, Leuven, Belgium The requirements of next-generation wireless terminals are driving RFIC design toward ubiquitous multistandard connectivity at reduced power consumption and cost [1-3]. While the use of scaled CMOS technology is required to allow economically feasible single-chip integration with a digital processor, a Software-Defined Radio (SDR) is the preferred approach to provide a reconfigurable platform, that covers a broad range of noise/linearity specifications while offering the best power/performance trade-off [4,5]. A 0.1-to-5GHz SDR receiver, including LO generation, has been developed in a 45nm CMOS technology (Fig. 24.1.1). To be competitive with dedicated single-mode radios, this SDR combines the most demanding requirements such

👥 作者与机构

Vito Giannini1, Pierluigi Nuzzo1, Charlotte Soens1,