A 7.2mW Quadrature GPS Receiver in 0.13µm CMOS

📋 论文概要

该论文提出了一种全集成低中频GPS接收机前端，采用0.13µm CMOS工艺，总功耗仅7.2mW，比以往设计降低约3倍。通过电流复用的堆叠正交LNA-混频器-VCO (QLMV)单元和连续时间正交ΔΣ ADC等创新技术，实现了超低功耗的GPS接收方案。

💡 主要创新点

• 提出电流复用的堆叠正交LNA-混频器-VCO (QLMV)单元，显著降低RF前端功耗。
• 采用连续时间正交ΔΣ ADC，实现低功耗高精度模数转换。
• 全集成低中频接收机架构，优化各模块功耗分配，整体功耗仅7.2mW。

🏷 关键词

📄 原文摘要

New design techniques are needed for ultra-low-power battery-operated CMOS transceivers with ever-shrinking minimum feature sizes and power supply voltages. A fully-integrated low-IF receiver front-end for GPS applications (Fig. 24.8.1) is presented that addresses this challenge. Integrated in 0.13µm CMOS, its key attribute is ~3X lower power than any previous design: The RF front-end, PLL, IF amplifiers and continuous-time (CT) quadrature ∆Σ ADC consume 1mW, 0.2mW, 1mW, and 5mW, respectively. The RF front-end exploits current reuse in a stacked quadrature LNA-mixer-VCO (QLMV) cell

👥 作者与机构

Kuang-Wei Cheng, Karthik Natarajan, David Allstot

University of Washington, Seattle, WA