Conditional Push-Pull Pulsed Latches with 726fJ·ps Energy-Delay Product in 65nm CMOS

📋 论文概要

该论文提出了一种条件推挽脉冲锁存器（Conditional Push-Pull Pulsed Latch），旨在降低触发器的能量延迟积（EDP）。在65nm CMOS工艺下实现了726fJ·ps的EDP，解决了高速低功耗微处理器中触发器能效优化的问题。

💡 主要创新点

• 提出条件推挽结构，通过动态控制驱动强度来减少冗余功耗，同时保持高速性能。
• 采用脉冲锁存器架构，结合推挽输出级，在宽设计空间内实现优于传统传输门脉冲锁存器（TGPL）的能效。

🏷 关键词

📄 原文摘要

University of Siena, Siena, Italy 3 University of Michigan, Ann Arbor, MI 4 University of California at Berkeley, Berkeley, CA 1 2 Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor’s clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large portion of the design space, ranging from high speed (minimizing EDj products with j>1) to minimum ED product designs

👥 作者与机构

Elio Consoli1, Massimo Alioto2,3, Gaetano Palumbo1, Jan Rabaey4

University of Catania, Catania, Italy