13% Power Reduction in 16b Integer Unit in 40nm CMOS by Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO

📋 论文概要

该论文提出了一种基于奇偶校验的自适应电源电压控制技术，用于40nm CMOS工艺的16位整数单元，通过动态调整电压以补偿工艺、电压和温度变化，实现了13%的功耗降低。解决了超低电压下电路延迟对PVT变化敏感导致需要过大时序余量的问题。

💡 主要创新点

• 提出利用奇偶校验进行错误预测，实现低成本的自适应电压调节，避免了传统冗余电路或时序监测的高开销。
• 在40nm CMOS整数单元中验证了该技术，在保持功能正确的前提下显著降低了功耗。

🏷 关键词

📄 原文摘要

Scaling power supply voltages (VDD’s) of logic circuits down to the sub/nearthreshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower VDD, adaptive VDD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive VDD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed. In conventional adaptive VDD control systems [1], a critical-path replica is used

👥 作者与机构

Koji Hirairi1, Yasuyuki Okuma1, Hiroshi Fuketa2, Tadashi Yasufuku2,

Makoto Takamiya2, Masahiro Nomura1, Hirofumi Shinohara1, Takayasu Sakurai2 Semiconductor Technology Academic Research Center, Tokyo, Japan, University of Tokyo, Tokyo, Japan 1 2