A 530mV 10-Lane SIMD Processor with Variation Resiliency in 45nm SOI

📋 论文概要

该论文提出了一种在45nm SOI工艺下工作的530mV 10通道SIMD处理器，通过Razor错误检测等三种机制来降低对工艺和动态变化的敏感性，解决了低电压操作下延迟退化和时序不确定性问题。

💡 主要创新点

• 采用Razor错误检测与恢复机制，实现时序误差的实时纠正，提升变化弹性。
• 通过架构级设计（如10通道SIMD并行处理）优化低电压下的吞吐量，减少延迟退化影响。

🏷 关键词

📄 原文摘要

exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-VDD operation: degraded logic delay resulting in significantly lower throughput than at super-threshold, and excessive, unpredictable delay variation caused by increased sensitivity to process and dynamic variations. We present the Synctium-I parallel SIMD (single-instruction multiple-data) processor, specifically architected to minimize susceptibility to process variations and timing uncertainty using three mechanisms: 1) Razor error detection and recovery [3] for each lane; 2) decoupling queues that prevent error events in any single lane from stalling all other lanes [4]; 3) lane weaving that enables

👥 作者与机构

Robert Pawlowski1, Evgeni Krimer2, Joseph Crop1, Jacob Postman1,

Nariman Moezzi-Madani3, Mattan Erez2, Patrick Chiang1 Oregon State University, Corvallis, OR University of Texas, Austin, TX 3 Qualcomm, San Diego, CA 1 2 Near-threshold computing