⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种41相开关电容电源转换器，在90nm CMOS工艺中实现了3.8mV输出纹波和81%的效率，解决了片上电源转换中电感集成困难的问题。
density of 38.6mW/mm2 at 81% efficiency and 3.8mV output voltage ripple (ΔVo) in baseline 90nm CMOS. The design implements two different conversion ratios to maximize efficiency for a wide range of input voltages, and the use of 41 phases results in a very low output voltage ripple and low input current spikes. Integrated SCPC have recently proved to be a feasible way to enable highly-efficient power conversion on-chip because they do not need integrated inductors (difficult to implement in standard CMOS technologies), specially for power levels below 100mW [1]. Figure 5.4.1 shows the peak efficiency versus power density reported in previous works [1]. The dashed black line represents the border of the current state-of-the-art designs implemented in CMOS without the use of SOI or deep trench capacitors. As observed, this work positions above this boundary. There are three different parameters to consider and optimize when designing an
NXP Semiconductors, Eindhoven, The Netherlands, This work presents a switched-capacitor power converter (SCPC) with a power