ISSCC 2013

2013

210 篇论文 · Wireless (34) · Memory (26) · Digital Circuits (17) · Medical & Bio (17) · Wireline I/O (17)

ISSCC 2013 Session 21 Power Management
A 93% Efficiency Reconfigurable Switched-Capacitor DC-DC Converter Using On-Chip Ferroelectric Capacitors
Dina El-Damak, Saurav Bandyopadhyay, Anantha P. Chandrakasan
Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacit
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2013 Session 21 Power Management
A Soft Self-Commutating Method Using Minimum Control Circuitry for Multiple-String LED Drivers
Junsik Kim, Jiyong Lee, Shihong Park
Light-emitting diodes (LEDs) are widely used in general lightings due to their several advantages including high efficiency, high reliability, long life, and environmental friendliness. Recently, various converter-free m
Dankook University, Yongin, Korea
ISSCC 2013 Session 22 Sensors
A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control
Vladimir P Petkov1, Ganesh K Balachandran1, Jochen Beintner2
in a broad range of vehicles [1]. The demand for lower cost and higher integration continues to increase the performance requirements for many of the system’s components. In particular, the trend towards placing the Iner
Robert Bosch, Palo Alto, CA, Robert Bosch, Reutlingen, Germany 1 2 Ele
ISSCC 2013 Session 22 Sensors
A 0.25mm2 AC-Biased MEMS Microphone Interface with 58dBA SNR
Selcuk Ersoy1, Robert H.M. van Veldhoven1, Fabio Sebastiano1,
Klaus Reimann1, Kofi A.A. Makinwa2 NXP Semiconductors, Eindhoven, The Netherlands, Delft University of Technology, Delft, The Netherlands 1 On-chip capacitors C1,2,3 must be trimmed to Cm to maximize carrier suppression
ISSCC 2013 Session 22 Sensors
A 0.5V <4μW CMOS Photoplethysmographic Heart-Rate Sensor IC Based on a Non-Uniform Quantizer
Mohammad Alhawari1,2, Nadya Albelooshi1, Michael H. Perrott1
Now at Khalifa University, Abu Dhabi, United Arab Emirates 1 2 Photoplethysmographic biosensing has been of recent interest, since it provides electrode-free operation for continuous health-monitoring applications [1]. T
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emi
ISSCC 2013 Session 22 Sensors
A Micropower Battery Current Sensor with ±0.03% (3σ) Inaccuracy from -40 to +85°C
Saleh Heidary Shalmany1, Dieter Draxelmayr2, Kofi A.A. Makinwa1
Infineon Technologies, Villach, Austria 1 2 This paper presents a micropower current-sensing system (CSS) for battery monitoring, which consists of a calibrated shunt resistor, a ΔΣ ADC, and a dynamic bandgap reference (
Delft University of Technology, Delft, The Netherlands,
ISSCC 2013 Session 22 Sensors
A 55dB SNR with 240Hz Frame Scan Rate Mutual Capacitor 30×24 Touch-Screen Panel Read-Out IC Using Code-Division Multiple Sensing Technique
Hyungcheol Shin1, Seunghoon Ko1, Hongjae Jang1, Ilhyun Yun2, Kwyro Lee1
interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poo
KAIST, Daejeon, Korea, Zinitix, Daejeon, Korea 1 2 Capacitive touch-sc
ISSCC 2013 Session 22 Sensors
A Highly Noise-Immune Touch Controller Using Filtered-Delta-Integration and a Charge-Interpolation Technique for 10.1-inch Capacitive Touch-Screen Panels
Jun-Hyeok Yang1, Sang-Hui Park1, Jung-Min Choi2, Hyun-Sik Kim1,
mobile products on the basis of their high quality of touch features, as well as superior visibility and durability [1-5]. Capacitive TSPs can be classified into selfcapacitance [1,2] or mutual-capacitance [3-5] types, a
Chang-Byung Park1, Seung-Tak Ryu1, Gyu-Hyeong Cho1 KAIST, Daejeon, Kor
ISSCC 2013 Session 22 Sensors
A 5.6mV Inter-Channel DVO 10b Column-Driver IC with Mismatch-Free Switched-Capacitor Interpolation for Mobile Active-Matrix LCDs
Hyun-Sik Kim, Jun-Hyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho
resolution and good channel-to-channel uniformity are required in column-driver ICs. In conventional column-driver ICs, the resistor-DAC (R-DAC) architecture has been generally used due to its uniform characteristic, bec
KAIST, Daejeon, Korea To achieve high image quality in mobile active-m
ISSCC 2013 Session 22 Sensors
A [10°C ; 70°C] 640×480 17μm Pixel Pitch TEC-Less IR Bolometer Imager with Below 50mK and Below 4V Power Supply
The CTIA’s gain can be set between 5 and 70V/μA. At 30°C, such a high gain, allows for an output NETD that is only 2% hi
bolometer’s NETD. Bertrand Dupont, Antoine Dupret, Sebastien Becker, Antoine Hamelin, Fabrice Guellec, Pierre Imperinetti, Wilfried Rabaud To compensate for the remaining FPN, offset pre-correction (OPC) is implemented:
ISSCC 2013 Session 22 Sensors
3D Volumetric Ultrasound Imaging with a 32×32 CMUT Array Integrated with Front-End ICs Using Flip-Chip Bonding Technology
Anshuman Bhuyan1, Jung Woo Choe1, Byung Chul Lee1, Ira Wygant2,
Amin Nikoozadeh1, Omer Oralkan3, Butrus T. Khuri-Yakub1 Stanford University, Stanford, CA, Texas Instruments, Santa Clara, CA, 3 North Carolina State University, Raleigh, NC 1 2 3D ultrasound imaging is becoming increasi
ISSCC 2013 Session 23 Clocking & PLLs
A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI
Yong Liu1, Ping-Hsuan Hsieh*, Seongwon Kim1, Jae-sun Seo1,
J. Watson, Yorktown Heights, NY, in transparent mode and the other is in data latching mode. The output stability is improved by newly-introduced weak pull-up transistor M7 that helps maintain the voltage level of node G
Robert Montoye1, Leland Chang1, Jose Tierno**, Daniel Friedman1 IBM T
ISSCC 2013 Session 23 Clocking & PLLs
A Scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-Lane Parallel I/O in 32nm CMOS
Mozhgan Mansuri1, James E. Jaussi1, Joseph T. Kennedy1,
Tzu-Chien Hsueh1, Sudip Shekhar1, Ganesh Balamurugan1, Frank O’Mahony1, Clark Roberts1, Randy Mooney2, Bryan Casper1 Intel, Hillsboro, OR, 2Intel, Mapleton, UT 1 High-performance computing (HPC) systems demand aggressive
ISSCC 2013 Session 23 Clocking & PLLs
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
John W. Poulton1, William J. Dally2, Xi Chen2, John G. Eyles1,
Thomas H. Greer III1, Stephen G. Tell1, C. Thomas Gray1 The receiver (right of Fig. 23.3.2) consists of a common-gate amplifier [3,4], biased so that its output swing is symmetric around the switching threshold of a CMOS
ISSCC 2013 Session 23 Clocking & PLLs
A 5.5Gb/s 5mm Contactless Interface Containing a 50Mb/s Bidirectional Sub-Channel Employing Common-Mode OOK Signaling
Ken’ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno
replace existing interfaces that use wire harnesses and connectors, are expected to be employed in many applications because they would provide such features as immunity to mechanical failures due to vibration/friction,
Renesas Electronics, Kawasaki, Japan High-volume, mm-range, contact-le
ISSCC 2013 Session 23 Clocking & PLLs
An 8Gb/s 1.5mW/Gb/s 8-Tap 6b NRZ/PAM-4 Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22nm CMOS
Marcel Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Brändli,
feed-forward equalization (FFE)
Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Th
ISSCC 2013 Session 23 Clocking & PLLs
An 8Gb/s 0.65mW/Gb/s Forwarded-Clock Receiver Using an ILO with Dual Feedback Loop and Quadrature Injection Scheme
Ji-Hwan Seol1, Young-Ju Kim1, Sang-Hye Chung1, Kyoung-Soo Ha2,
low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data j
Seung-Jun Bae2, Jung-Bae Lee2, Joo Sun Choi2, Lee-Sup Kim1 KAIST, Daej
ISSCC 2013 Session 23 Clocking & PLLs
A 3.1mW Phase-Tunable Quadrature-Generation Method for CEI 28G Short-Reach CDR in 28nm CMOS
Kanupriya Bhardwaj1, Sriram Narayan2, Sergey Shumarayev3, Thomas Lee1
phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature gener
Stanford University, Stanford, CA, Inphi, Santa Clara, CA, 3 Altera, S
ISSCC 2013 Session 23 Clocking & PLLs
A Divider-Less Sub-Harmonically Injection-Locked PLL with Self-Adjusted Injection Timing
I-Ting Lee1, Yen-Jen Chen2, Shen-Iuan Liu1, Chewn-Pu Jou2,
frequency synthesis, and data conversion. In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In [3-5], a low-phase-noise sub-harmonically injection-locked PL
Fu-Lung Hsueh2, Hsieh-Hung Hsieh2 National Taiwan University, Taipei,
ISSCC 2013 Session 23 Clocking & PLLs
A Wideband Fractional-N Ring PLL with FractionalSpur Suppression Using Spectrally Shaped Segmentation
Tsung-Kai Kao1, Che-Fu Liang1, Hsien-Hsiang Chiu1, Michael Ashburn2
Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI)
MediaTek, Hsinchu, Taiwan, 2MediaTek, Woburn, MA
ISSCC 2013 Session 24 Digital Circuits
A 1.15Gb/s Fully Parallel Nonbinary LDPC Decoder with Fine-Grained Dynamic Clock Gating
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signalto-noise ratio (SNR). State-of-the-art channel codes including tu
University of Michigan, Ann Arbor, MI
ISSCC 2013 Session 24 Digital Circuits
Ultra-Wide Body-Bias Range LDPC Decoder in 28nm UTBB FDSOI Technology
Philippe Flatresse1, Bastien Giraud2, Jean-Philippe Noel1,
Bertrand Pelloux-Prayer1, Fabien Giner1, Deepak-Kumar Arora3, Franck Arnaud1, Nicolas Planes1, Julien Le Coz1, Olivier Thomas2, Sylvain Engels1, Giorgio Cesana1, Robin Wilson1, Pascal Urard1 STMicroelectronics, Crolles,
ISSCC 2013 Session 24 Digital Circuits
Self-Super-Cutoff Power Gating with State Retention on a 0.3V 0.29fJ/Cycle/Gate 32b RISC Core in 0.13μm CMOS
Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang
Using ultra low-voltage (ULV) is a viable approach towards lowering power consumption. However, due to the narrowing gap between the supply voltage and the threshold voltage, ULV designs inevitably suffer from either low
National Chung Cheng University, Chaiyi, Taiwan
ISSCC 2013 Session 24 Digital Circuits
A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS
Paul N. Whatmough, Shidhartha Das, David M. Bull
ARM, Cambridge, United Kingdom The unrelenting demands of wireless/multimedia DSP workloads necessitate specialized hardware to achieve higher performance and power efficiency. Razor systems offer even greater power effi
ISSCC 2013 Session 24 Digital Circuits
Reliable and Energy-Efficient 1MHz 0.4V Dynamically Reconfigurable SoC for ExG Applications in 40nm LP CMOS
Mario Konijnenburg1, Yeongojn Cho2, Maryam Ashouei1,
Tobias Gemmeke1, Changmoo Kim2, Jos Hulzink1, Jan Stuyt1, Mookyung Jung2, Jos Huisken1, Soojung Ryu2, Jungwook Kim2, Harmke de Groot1 imec - Holst Centre, Eindhoven, The Netherlands, Samsung Advanced Institute of Technol
ISSCC 2013 Session 24 Digital Circuits
An 8MHz 75μA/MHz Zero-Leakage Non-Volatile Logic-Based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400ns Wakeup and Sleep Transitions
Steven C. Bartling, Sudhanshu Khanna, Michael P. Clinton,
Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams Texas Instruments, Dallas, TX We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt,
ISSCC 2013 Session 24 Digital Circuits
A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing
Satoshi Takaya1, Makoto Nagata1, Atsushi Sakai2, Takashi Kariya2,
dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power
Shiro Uchiyama2, Harufumi Kobayashi2, Hiroaki Ikeda2 Kobe University,
ISSCC 2013 Session 24 Digital Circuits
Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits
Hiroshi Fuketa1, Masahiro Nomura2, Makoto Takamiya1, Takayasu Sakurai1
37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static
University of Tokyo, Tokyo, Japan, Semiconductor Technology Academic R
ISSCC 2013 Session 25 Wireless
A 45nm CMOS Near-Field Communication Radio with 0.15A/m RX Sensitivity and 4mA Current Consumption in Card Emulation Mode
Yogesh Darwhekar1, Evgeniy Braginskiy2, Koby Levy2,
Abhishek Agrawal1, Vikas Singh1, Ronen Issac2, Ofer Blonskey2, Ofer Adler2, Yoav Benkuzari2, Matan Ben-Shachar2, Srikanth Manian1, Apu Sivadas1, Subhashish Mukherjee1, Gangadhar Burra3, Nir Tal2, Yariv Shlivinski2, Guy B
ISSCC 2013 Session 25 Wireless
A Super-Regenerative Radio on Plastic Based on Thin-Film Transistors and Antennas on Large Flexible Sheets for Distributed Communication Links
Liechao Huang, Warren Rieutort-Louis, Yingzhe Hu,
Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma Princeton University, Princeton, NJ Large-area electronics presents new form factors, enabling ubiquitous systems that are flexible and capable of scaling
ISSCC 2013 Session 25 Wireless
An Ultra-Low-Power 9.8GHz Crystal-Less UWB Transceiver with Digital Baseband Integrated in 0.18µm BiCMOS
Jonathan K. Brown1, Kuo-Ken Huang2, Elnaz Ansari2, Ryan R. Rogel2,
Yoonmyung Lee2, David D. Wentzloff2 Cavium, Marlborough, MA, University of Michigan, Ann Arbor, MI T, to trigger the switching threshold, VH, so that the overall period remains unchanged. The comparator consists of two s
ISSCC 2013 Session 25 Wireless
A Self-Duty-Cycled and Synchronized UWB Receiver SoC Consuming 375pJ/b for -76.5dBm Sensitivity at 2Mb/s
Baradwaj Vigraham, Peter Kinget
Novel highly networked applications with severe energy constraints such as tag and body-area networks, for ubiquitous object networking [1] or the ‘Internet of Things’ are driving the need for ultra-low-power wireless da
Columbia University, New York, NY
ISSCC 2013 Session 25 Wireless
A 1.9nJ/b 2.4GHz Multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) Transceiver for Personal/Body-Area Networks
Yao-Hong Liu1, Xiongchuan Huang1, Maja Vidojkovic1, Ao Ba1,
multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) an
Pieter Harpe2, Guido Dolmans1, Harmke de Groot1 imec - Holst Centre, E
ISSCC 2013 Session 25 Wireless
A 1.7mW 0.22mm2 2.4GHz ZigBee RX Exploiting a Current-Reuse Blixer + Hybrid Filter Topology in 65nm CMOS
Zhicheng Lin1, Pui-In Mak1, Rui Martins1,2
Instituto Superior Tecnico, Lisbon, Portugal 1 A GHz-range div-by-2 is compact and wideband enough to generate a 4-phase LO with a duty cycle not necessarily 50%. Here, DIV1 accepts a 50%-duty-cycle 2-phase input, and de
University of Macau, Macao, China,
ISSCC 2013 Session 25 Wireless
A 110pJ/b Multichannel FSK/GMSK/QPSK/π/4-DQPSK Transmitter with Phase-Interpolated Dual-Injection DLL-Based Synthesizer Employing Hybrid FIR
San-Jeow Cheng1, Yuan Gao1, Wei-Da Toh1, Yuanjin Zheng2,
of Singapore, Singapore, Singapore 1 2 The IEEE 802.15.6 Wireless Body-Area-Network (WBAN) standard has recently specified narrowband (NB) PHY covering GMSK and D-PSK modulations targeted at varying data rates [1]. There
Minkyu Je1,3, Chun-Huat Heng3 Institute of Microelectronics, Singapore
ISSCC 2013 Session 25 Wireless
A 5.5mW IEEE-802.15.6 Wireless Body-AreaNetwork Standard Transceiver for Multichannel Electro-Acupuncture Application
Hyungwoo Lee, Kwonjoon Lee, Sunjoo Hong, Kiseok Song,
the human body is the key technology for continuous, automated, and unobtrusive monitoring of physiological signals. Recently, the IEEE Standards Association established a wireless body-area-network (WBAN) standard for a
Taehwan Roh, Joonsung Bae, Hoi-Jun Yoo KAIST, Daejeon, Korea Ultra-low
ISSCC 2013 Session 25 Wireless
Wideband UHF ISM-Band Transceiver Supporting Multichannel Reception and DSSS Modulation
Jan van Sinderen1, Gerben W de Jong1, Frank Leong1, Xin He1,
Melina Apostolidou1, Harish Kundur Subramaniyan1, Robert Rutten1, Jan Niehof1, Jos Verlinden1, Hao Wang1, Anton Hoogstraate1, Ka Chun Kwok1, Rene Verlinden1, Reinier Hoogendoorn1, Dennis Jeurissen2, Anton Salfelner2, Ewa
ISSCC 2013 Session 25 Wireless
A 1.6mW 300mV-Supply 2.4GHz Receiver with -94dBm Sensitivity for Energy-Harvesting Applications
Fan Zhang1, Keping Wang1, Jabeom Koo1, Yasunori Miyahara2, Brian Otis1
9.3 shows the schematic of the IF-chain. Due to the severe headroom limitation, we used two single-ended self-biased inverters instead of OTAs as IF amplifiers. Compared to a conventional common-source stage, this curren
University of Washington, Seattle, WA, 2Panasonic, Yokohama, Japan Fig
ISSCC 2013 Session 26 Data Converters
A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications
Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos,
throughout the network infrastructure. A wide array of standards has been developed supporting 10GE over both fiber and copper media. A particularly challenging standard is Long Reach Multimode (LRM), which targets insta
Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropo
ISSCC 2013 Session 26 Data Converters
An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS
Erwin Janssen1, Kostas Doris1, Athon Zanikopoulos1,
Alessandro Murroni1, Gerard van der Weide1, Yu Lin1, Ludo Alvado2, Frederic Darthenay2, Yannick Fregeais2 NXP Semiconductors, Eindhoven, The Netherlands, NXP Semiconductors, Caen, France 1 2 Over the last years several l
ISSCC 2013 Session 26 Data Converters
A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction the chop PRBS. BUF1 and BUF2 modulate the chop drive signal at the bases of Q1–Q4 with a level-shifted version of the input signal. This bootstrapping ensures that M1 and M2 have a reasonably constant Vgd for improved linearity and reduced thermal transients.
Brian Setterberg1, Ken Poulton1, Sourja Ray1, Dan J. Huber1,
Valentin Abramzon1, Guenter Steinbach1, John P. Keane1, Bernd Wuppermann1, Mathew Clayson1, Matthew Martin2, Rizwan Pasha2, Edda Peeters3, Annemie Jacobs3, Filip Demarsin3, Adnan Al-Adnani3, Peter Brandt3 The analog dith
ISSCC 2013 Session 26 Data Converters
A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
Lukas Kull1,2, Thomas Toifl1, Martin Schmatz1, Pier Andrea Francese1,
Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, 2EPFL, Lausanne, Switzerland 1 Next-generation digital high-speed links
ISSCC 2013 Session 26 Data Converters
An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement
Hyeok-Ki Hong1, Hyun-Wook Kang1, Barosaim Sung1,
consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in
Choong-Hoon Lee2, Michael Choi2, Ho-Jin Park2, Seung-Tak Ryu1 KAIST, D
ISSCC 2013 Session 26 Data Converters
A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
Ron Kapusta1, Junhua Shen1, Steven Decker1, Hongxing Li2, Eitake Ibaragi2
veryhigh-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings [1], and (b) in high-speed, lowresolution applications [2, 3] in which the SAR’s low power
Analog Devices, Wilmington, MA, 2Analog Devices, Tokyo, Japan 1 Succes
ISSCC 2013 Session 26 Data Converters
A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over Entire Nyquist Bandwidth
Wei-Te Lin, Tai-Haur Kuo
Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at t
National Cheng Kung University, Tainan, Taiwan
ISSCC 2013 Session 27 Image Sensors
A 3.4μW CMOS Image Sensor with Embedded Feature-Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging
Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon
Distributed sensor nodes typically operate under the constraint of limited energy source, and power consumption is an important factor to extend the lifetime of sensor systems. Several low-power imagers have been reporte
University of Michigan, Ann Arbor, MI
ISSCC 2013 Session 27 Image Sensors
A 467nW CMOS Visual Motion Sensor with Temporal Averaging and Pixel Aggregation
Gyouho Kim, Mahmood Barangi, Zhiyoong Foo, Nathaniel Pinckney,
variety of new applications for wireless sensor nodes, ranging from military surveillance to in vivo molecular imaging. In particular, the ability to detect motion can enable more intelligent power management through on-
Suyoung Bang, David Blaauw, Dennis Sylvester University of Michigan, A
ISSCC 2013 Session 27 Image Sensors
A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node
Jun Aoki, Yoshiaki Takemoto, Kenji Kobayashi, Naofumi Sakaguchi,
Mitsuhiro Tsukimura, Naohiro Takazawa, Hideki Kato, Toru Kondo, Haruhisa Saito, Yuichi Gomi, Yoshitaka Tadaki Olympus, Hachioji, Japan Conventional CMOS image sensors widely used in products currently on the market are m
ISSCC 2013 Session 27 Image Sensors
A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor
Shunichi Sukegawa1, Taku Umebayashi1, Tsutomu Nakajima1,
Hiroshi Kawanobe1, Ken Koseki2, Isao Hirota1, Tsutomu Haruta1, Masanori Kasai1, Koji Fukumoto1, Toshifumi Wakano1, Keishi Inoue3, Hiroshi Takahashi1, Takashi Nagano1, Yoshikazu Nitta1, Teruo Hirayama1, Noriyuki Fukushima
ISSCC 2013 Session 27 Image Sensors
An 8×16-pixel 92kSPAD Time-Resolved Sensor with On-Pixel 64ps 12b TDC and 100MS/s Real-Time Energy Histogramming in 0.13μm CIS Technology for PET/MRI Applications
Leo Huf Campos Braga1, Leonardo Gasparini1, Lindsay Grant2,
Robert K. Henderson3, Nicola Massari1, Matteo Perenzoni1, David Stoppa1, Richard Walker3 Fondazione Bruno Kessler, Trento, Italy, STMicroelectronics, Edinburgh, United Kingdom, 3 University of Edinburgh, Edinburgh, Unite