ISSCC 2018
Session 25
Wireline I/O
A 5GHz 370fsrms 6.5mW Clock Multiplier Using a Crystal-Oscillator Frequency Quadrupler in 65nm CMOS
(RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (
ISSCC 2017
Session 8
Digital Circuits
A 2.5-to-5.75GHz 5mW 0.3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS
traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter r