机构

ETH Zurich

6 篇 ISSCC 论文

ISSCC 2026 Session 29 Medical & Bio
Shape-Memory Multi-Size Micro-Cage Array on CMOS with Integrated Electrochemical Sensors for Joint Bio-Sample Manipulation and Sensing
Zhikai Huang, Fuze Jiang, Hangxing Liu, Adam Wang, Yuguo Sheng, Marco Saif, Hua Wang
Abstract Lab-on-CMOS platforms require joint sensing–manipulation capabilities for biosamples from single cells to organoids. Existing methods such as DEP, optical, and acoustic tweezers need external setups, continuous
ISSCC 2026 Session 20 RF & Wireless
An Ultra-Compact Asymmetrically Load-Pulled Series Doherty Power Amplifier in 22nm FDSOI CMOS with 25.3dBm Psat and 29.7% PAE6dB for Ku-Band 6G FR3
Jinglong Xu1, Tzu-Yuan Huang1,2, Mohamed Eleraky1, Islam Tolaib1, Hua Wang1
Abstract This paper presents an ultra-compact asymmetrically load-pulled series Doherty PA in 22nm CMOS SOI with a single-footprint output combiner. A quantitative analysis of a single transformer as an impedance inverte
ISSCC 2024 Session 32 AI / ML
An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer Output Combiner
Edward Liu1,2, Hua Wang1
Georgia Institute of Technology, Atlanta, GA 1 2 Mm-wave wireless communication and sensing heavily rely on phased arrays to compensate for high path losses and meet link-budget targets. Recent mm-wave arrays have grown
ISSCC 2024 Session 32 Power Management
A Compact Broadband VSWR-Resilient True-Power-and-Gain Sensor with Dynamic-Range Compensation for Phased-Array Applications
Edward Liu*1, David Munzer*2, Jeongseok Lee2, Hua Wang1
Georgia Institute of Technology, Atlanta, GA *Equally Credited Authors (ECAs) 1 2 With the rapid growth of mm-wave wireless technologies, phased arrays are essential to meet the stringent link-budget requirements under p
ISSCC 2021 Session 17 Power Management
A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Alessandro Novello1, Gabriele Atzeni1, Giorgio Cristiano1, Mathieu Coustans2, Taekwang Jang1
electronics has strengthened the demand for fully integrated power management circuits. Buck converters offer high efficiency, but they cannot satisfy the stringent size requirements because bulky off-chip inductors are
ISSCC 2008 Session 13 Digital Processors
A 58mW 1.2mm² HSDPA Turbo Decoder ASIC in 0.13µm CMOS
Christian Benkeser1, Andreas Burg1, Teo Cupaiuolo1, Qiuting Huang1,2, 1
provide a compelling user experience has made HSPA an indispensable catalyst for a substantial subscriber transition from 2G to 3G [1]. Data rates reaching the full potential of 3GPP R6 from cost-effective mobile termina