机构

Herschel Ainspan

2 篇 ISSCC 论文

ISSCC 2016 Session 10 Wireline I/O
A 12-to-26GHz Fractional-N PLL with Dual Continuous Tuning LC-D/VCOs
Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov,
key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2]
ISSCC 2015 Session 10 Wireline I/O
A 13.1-to-28GHz Fractional-N PLL in 32nm SOI CMOS with a ΔΣ Noise-Cancellation Scheme
Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov,
as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range application