Institute of Semiconductors — ISSCC 知识库

ISSCC 2026 Session 8 Wireline I/O

A 112Gb/s 0.76pJ/b Reference-less Mixed-Signal PAM-4 CDR in 28nm CMOS

Zhaoyu Zhang*1,2, Yiqing Xu*1,2, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2

*Equally Credited Authors (ECAs) 1 Abstract This paper presents a 112Gb/s mixed-signal reference-less PAM-4 CDR in 28nm CMOS. By proposing the hybrid architecture based on a symmetrical linear PD and a bang-bang PFD, a f

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, Chi

ISSCC 2026 Session 12 Clocking & PLLs

A 0.65-to-1V-VDD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS

Yixi Li1,2, Junjie Chen1,2, Xinyu Shen1, Jie Yang3, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2

Abstract This paper presents a 0.65-to-1V, 10.5-to-11.85GHz wide-VDD-range (WV) fractional-N sampling PLL. The QE-reduction WV SPD, high-linearity 2-stage DTC, and DCC-aided QE dithering method are proposed to address th

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, Chi