ISSCC 2015
Session 15
Data Converters
A 0.6V 1.17ps PVT-Tolerant and Synthesizable Time-to-Digital Converter Using Stochastic Phase Interpolation with 16× Spatial Redundancy in 14nm FinFET Technology
timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of qu
ISSCC 2013
Session 14
Digital Circuits
A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter
from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from