ISSCC 2024
Session 9
Data Converters
A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm We introduce an extra CC path (shaded blocks in Fig. 9.6.3) to the integrator within NSSAR to achieve even higher SNR. This transforms the NTF of the NSSAR to the desired band, resulting in further suppressed quantization noise in the target bandwidth. Figure 9.6.3 shows the effectiveness of our QNSSAR with the simulated quantization noise using three different quantizers in a quadrature CT-DSM with ideal models. The resulting SQNR utilizing QNSSAR is 93.52dB while the conventional SAR, and NSSAR give 76.35dB, and 88.36dB, respectively.
low-intermediatefrequency (low-IF) architecture is widely chosen for energy efficient wireless communication systems, such as Bluetooth Low Energy (BLE) and IoT. The low-IF architecture typically requires filters for anti-
ISSCC 2024
Session 9
Data Converters
A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm
energy-efficient alternatives to OTAs for switchedcapacitor residue amplifiers. A ring amplifier is essentially a cascaded multi-stage inverter-based amplifier that is stabilized by a dominant pole at the last stage output w
ISSCC 2024
Session 14
Digital Circuits
A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET
by CPU cluster to simplify the PMIC-SoC power rails in limited PCB area (VDDLIT, VDDMID and VDDBIG in Fig. 14.6.1). In order to optimize the power of each CPU core, integrated LDOs (iLDO) have recently been proposed [1-4