ISSCC 2016
Session 20
RF & Wireless
A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers
seeks to address several key challenges of 4G and 5G mobile systems [1]. The basic principle is shown in Fig. 20.8.1. Duplexer isolation is achieved when the signals in paths 1 and 2 cancel and prevent the TX signal from
ISSCC 2010
Session 16
Data Converters
A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS
fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed w
ISSCC 2009
Session 22
RF & Wireless
50-to-67GHz ESD-Protected Power Amplifiers in Digital 45nm LP CMOS
shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with t