50-to-67GHz ESD-Protected Power Amplifiers in Digital 45nm LP CMOS

📋 论文概要

本文在数字45nm低功耗CMOS工艺中设计并实现了50-67GHz的ESD保护功率放大器，解决了先进数字CMOS工艺中后端互连层薄导致无源器件Q值低、以及需要集成ESD保护的挑战，展示了该工艺用于60GHz无线通信收发器的可行性。

💡 主要创新点

• 在45nm数字低功耗CMOS中实现了宽带（50-67GHz）的功率放大器，充分利用了该工艺的高ft特性。
• 集成了ESD保护结构，同时保持射频性能，解决了毫米波频段ESD保护的难题。
• 通过优化设计克服了薄金属层带来的无源器件品质因数下降问题，实现了与先进数字工艺的兼容。

🏷 关键词

📄 原文摘要

shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with the transceiver onto a single chip. The complexity of the digital part demands a very advanced CMOS technology, such as 45nm low-power (LP) CMOS. Although this technology features a high maximum fT, above 200GHz, the back-end-of-line (BEOL) metallization layers are thinner than in less-advanced technology. This implies a lower quality factor for the passive components and a lower intrinsic ESD robustness due to a higher sheet resistance of the metal layers. These restrictions, together with the limited power capabilities of CMOS make the design of mm-wave power amplifiers (PAs) more challenging [3,4].

👥 作者与机构

Kuba Raczkowski1,2, Steven Thijs1,2, Walter De Raedt1, Bart Nauwelaers2,

Piet Wambacq1,3 1 IMEC, Leuven, Belgium, KU Leuven, Leuven, Belgium, 3 Vrije Universiteit Brussel, Brussels, Belgium 2 Research in recent years has