Ru Huang — ISSCC 知识库

ISSCC 2025 Session 18 Data Converters

An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration

Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan,

realized utilizing the energy-efficient pipelined-SAR architecture [1-2]. However, a large sampling capacitance is required to suppress the thermal noise, making ADCs challenging to drive. Although the integrated driving

Ru Huang, Linxiao Shen Peking University, Beijing, China High-resoluti

ISSCC 2025 Session 18 Data Converters

A 12.2µW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD ∆ΣM with Gain-Embedded Bootstrapped Sampler

Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye,

consumption as they determine the overall noise and linearity performance. To achieve high resolution, discrete-time (DT) ∆ΣMs require large sampling capacitors [1-3]. This induces a huge driving burden for the ADC input

Ru Huang, Linxiao Shen Peking University, Beijing, China Input stages