ISSCC 2017
Session 16
Data Converters
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration
Wireless communication systems and Ethernet networks call for moderateresolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardwar
ISSCC 2011
Session 10
Data Converters
A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS
Italy 2 The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS tech