University College Dublin — ISSCC 知识库

ISSCC 2026 Session 27 Clocking & PLLs

A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock

Jiawen Chen1,2, Kai Xu2, Luyi Guo1, Teerachot Siriburanon1, Jun Yin3, Bashir M. Al-Hashimi2, Robert Bogdan Staszewski1

Abstract This paper presents a 0.3V dual-mode (2.4/4.8GHz) DCO-PA for BLE, achieving 42% efficiency in the TX mode and 0.29mW power consumption in the RX clock mode. It features: 1) a twisted 8-shape inductor enabling oc

University College Dublin, Dublin, Ireland, 2King’s College London, Lo

ISSCC 2025 Session 19 Clocking & PLLs

An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

Jiawen Chen1, Kai Xu2, Teerachot Siriburanon1, Robert Bogdan Staszewski1

King’s College London, London, United Kingdom 1 2 As data-rate requirements in 5G-Advanced and future 6G communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring hi

University College Dublin, Dublin, Ireland