ISSCC 2022
Session 17
Wireline I/O
A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process
MaxLinear, Carlsbad, CA 1 2 Increased data-rates and multi-lane SerDes implementations impose stringent conditions for CDRs to produce low-jitter clocking that is capable of managing frequency and phase offsets. Conseque
ISSCC 2018
Session 15
RF & Wireless
A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with –254dB FOM
Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations a