ISSCC 2015
Session 26
Data Converters
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4×-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique
(TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching
ISSCC 2015
Session 26
Data Converters
A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS
taken advantage of timeinterleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexit