Adaptive Circuits for the 0.5-V Nanoscale CMOS Era Kiyoo Itoh

📋 论文概要

本文针对纳米尺度CMOS LSI中低电压缩放的功耗危机，分析了不可缩放阈值电压带来的限制，提出了自适应电路技术以实现0.5V操作，旨在克服亚阈值泄漏和性能退化问题。

💡 主要创新点

• 提出了自适应阈值电压控制技术，通过动态调整Vt来平衡泄漏与性能，支持亚1V操作。
• 引入了自适应体偏置和电源电压调节方法，在0.5V纳米CMOS时代保持电路鲁棒性。

🏷 关键词

📄 原文摘要

Low-voltage scaling limitations of memory-rich CMOS LSIs are one of the major problems in the nanoscale era [1-3] because they cause the evermore-serious power crises with device scaling. The problems stem from two unscalable device parameters: The first is the high value of the lowest necessary threshold voltage, Vt (that is,Vt0), of MOSFETs needed to keep the subthreshold leakage low. Although many intensive attempts to reduce Vt0 through reducing leakage have been made since the late 1980s [3-5], Vt0 is still not low enough to reduce the operating voltage, VDD, to the sub-1V region. The second is the variation in Vt (that is, ∆Vt), that becomes more prominent in the nanoscale era [1-3]. The ∆Vt caused by the intrinsic random dopant fluctuation (RDF) is the major source of various ∆Vt components. It increases with device scaling and thus enhances various detrimental effects such as variations in delay (and speed) and/or the voltage margins of circuits, and it significantly increases

👥 作者与机构

Fellow, Hitachi, Tokyo, Japan, 1. Introduction