A 4.75GHz Fractional Frequency Divider with Digital Spur Calibration in 45nm CMOS

📋 论文概要

该论文提出了一种工作在4.75GHz的分数分频器，通过引入分数分频比来避免收发机中本振被功率放大器牵引的问题。采用数字校准技术抑制分数杂散，从而无需额外的滤波电感，节省了芯片面积。

💡 主要创新点

• 采用分数分频比替代传统的二分频或SSB混频，有效避免本振牵引问题
• 通过数字校准技术抑制分数杂散，省去模拟滤波电感，节省面积

🏷 关键词

📄 原文摘要

transceivers. To offset the oscillator frequency from the PA output frequency, SSB mixing or division-by-2 is typically used [1]. However, the first might require additional filtering to remove mixing spurs and the latter is still sensitive to secondharmonic pulling. The divider described in this paper prevents LO pulling by introducing a fractional ratio between input and output frequencies. Since fractional spurs are suppressed by digital calibration, no additional filtering is required, removing inductors and saving silicon area. Figure 12.6.1 shows the block diagram of the divider and the timing chart of the main signals. A 9.5GHz divide-by-2 generates 4 quadrature phases, ph1 to ph4. A pass-gate mux scans cyclically through them, stepping to the next one every period of the output signal LOout (timing chart in Fig. 12.6.1). This operation results in a div

👥 作者与机构

Stefano Pellerano1, Paolo Madoglio2, Yorgos Palaskas1, 1

Intel, Hillsboro, OR Politecnico di Milano, Milan, Italy 2 Local-oscillator (LO) pulling is a typical issue in fully integrated