⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了采用34nm CMOS工艺实现的172mm²、32Gb多级单元(MLC)NAND闪存。该设计在保持较小芯片面积的同时实现了高存储密度，满足了成本敏感型市场对NAND闪存容量的持续增长需求。
Matt Goldman1, Chris Haid1, Atif Huq1, Takaaki Ichikawa2, Joel Jorgensen1, Owen Jungroth1, Nishant Kajla1, Ravinder Kajley1, Koichi Kawai2, Jiro Kishimoto2, Ali Madraswala1, Tetsuji Manabe2, Vikram Mehta1, Midori Morooka2, Katie Nguyen1, Yoko Oikawa2, Bharat Pathak1, Rod Rozman1, Tom Ryan1, Andy Sendrowski1, William Sheung1, Martin Szwarc1, Yasuhiro Takashima2, Satoru Tamada2, Toru Tanzawa2, Tomoharu Tanaka2, Mase Taub1, Darshak Udeshi1, Shigekazu Yamada2, Hiroyuki Yokoyama2 Intel, Folsom, CA Micron, Tokyo, Japan 1 2 As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements [1,2]. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device
Raymond Zeng1, Navneet Chalagalla1, Dan Chu1, Daniel Elmhurst1,