⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款采用48nm工艺的32Gb 8-level (3-bit per cell) NAND闪存芯片，实现了5.5MB/s的编程吞吐量，旨在降低每比特成本并提高存储密度，满足消费电子和固态硬盘等应用需求。
Jung-Chul Han, In-Soo Wang, kyu-hee Lim, Jung-Hwan Lee, Ji-Hwan Kim, Won-Kyung Kang, Tai-Kyu Kang, Hee-Su Byun, Yu-Jong Noh, Lee-Hyun Kwon, Bon-Kwang Koo, Myung Cho, Joong-Seob Yang, Yo-Hwan Koh Hynix Semiconductor, Icheon, Korea. Lower cost per bit and higher density NAND Flash memory is a general trend in nonvolatile memory applications, such as MP3 players, digital still cameras, video camcorders, USB memories and solid-state disk. Technology scaling has become expected from consumers and recently higher number of bits per cell, such as 8-level cell or 16-level cell, is becoming a viable alternative solution due to difficulties in scaling. However, a higher number of bits per cell has two technical hurdles to overcome. One is low program throughput and the other is insufficient VT-window margin. We design 32Gb 8-level NAND Flash memory with 5.5MB/s program performance that addresses these
Seung-Ho Chang, Sok-kyu Lee, Seong-Je Park, Min-Joong Jung,