A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

📋 论文概要

本文提出了一种用于NAND Flash存储器堆叠的电感耦合可编程总线，通过无线接口实现控制器与64个堆叠芯片的随机访问，数据率达2Gb/s，功耗为15pJ/b/chip。该技术利用中继传输和去除静电保护器件，显著降低了功耗和I/O电路面积。

💡 主要创新点

• 采用电感耦合无线接口替代传统有线连接，去除高电容ESD保护器件，功耗降低2倍，I/O电路面积减少40倍。
• 利用绑定线供电和无线数据访问，简化了芯片间互连，减少了绑定线数量。
• 通过中继传输实现控制器与堆叠中任意NAND Flash芯片的随机访问，支持64个芯片的高效通信。

🏷 关键词

📄 原文摘要

communication technique, which enables a controller chip to communicate with random access with a stack underneath it of 64 NAND Flash memory chips at a data rate of 2Gb/s using relayed transmission is developed (Fig. 13.5.1). This technique can be applied to memory access in solid-state drives (SSD). The wireless interface allows the removal of a highly capacitive ESD protection device and results in a 2× reduction in power consumption, and a 40× reduction in I/O circuit-layout area. Using bonding wires for the power supply and wireless interface for data access reduces the number of bonding wires in the 64-chip stack from over 1,500 wires to less than 200 wires. This reduction in the number of bonding wires makes it possible to integrate 64 chips in one package, which conventionally requires

👥 作者与机构

Yasufumi Sugimori1, Yoshinori Kohama1, Mitsuko Saito1,

Yoichi Yoshida1, Noriyuki Miura1, Hiroki Ishikuro1, Takayasu Sakurai2, Tadahiro Kuroda1 Keio University, Yokohama, Japan, University of Tokyo, Tokyo, Japan 1 2 A wireless