A 0.1e- Vertical FPN 4.7e- Read Noise 71dB DR CMOS Image Sensor with 13b Column-Parallel Single-Ended Cyclic ADCs

📋 论文概要

本文提出了一种采用13位列并行单端循环ADC的CMOS图像传感器，解决了列并行ADC架构带来的垂直固定模式噪声（VFPN）和读噪声问题。实现了0.1e-的垂直FPN、4.7e-的读噪声和71dB的动态范围。

💡 主要创新点

• 提出单端循环ADC列并行架构，有效降低垂直固定模式噪声和读噪声。
• 通过优化电路设计实现了极低的FPN（0.1e-）和读噪声（4.7e-），同时保持13位分辨率和71dB动态范围。

🏷 关键词

📄 原文摘要

Tomoyuki Akahori1, Tomohiko Kosugi1, Keigo Isobe1, Yuichi Kaneko1, Zheng Liu1, Kazuki Muramatsu1, Takeshi Matsuyama1, Shoji Kawahito1, 2 1 Brookman Lab, Hamamatsu, Japan, 2Shizuoka University, Hamamatsu, Japan The performance requirements of next-generation CMOS image sensors (CIS) have been increasing in terms of frame rate, read noise, dynamic range, as well as pixel resolution. In order to satisfy strict specifications, a columnparallel ADC is a key element in a state-of-the-art CIS. However, this architecture leads to side-effects such as vertical fixed pattern noise (VFPN) and read noise. In order to reduce these non-idealities, several techniques can be applied such as digital CDS using a single-slope ADC [1][2], and preamplified digital CDS using a SAR ADC [3]. It is challenging to overcome the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise performance and high dynamic range (DR). In this

👥 作者与机构

Jong-Ho Park1, Satoshi Aoyama1, Takashi Watanabe1,