An 18Gb/s Duobinary Receiver with a CDR-Assisted DFE

📋 论文概要

该论文提出了一种18Gb/s的duobinary接收器，采用CDR辅助的DFE技术来均衡信号。主要解决了duobinary信号中高频toggle pattern导致的DFE性能下降问题，通过CDR辅助机制改善了均衡效果。

💡 主要创新点

• 提出CDR辅助的DFE架构，利用时钟数据恢复信号增强均衡性能，尤其针对duobinary信号中toggle pattern导致的ISI衰减问题。
• 实现18Gb/s的高速duobinary接收，不需要传统ADC，降低了功耗和复杂度。
• 通过优化DFE系数和CDR环路，在无需额外模拟电路的情况下提升了接收器的抗ISI能力。

🏷 关键词

📄 原文摘要

As shown in Fig. 16.1.3, when the transmitter output patterns are especially toggle patterns (1010…), the received input data have intermediate voltages between VH and VL (or the slicer outputs (DH(T), DL(T)) consequently become (−1, +1)), so the DFE does not perform equalization. However, the ISI caused by toggle patterns is attenuated drastically and can be ignored because the frequencies of toggle patterns are sufficiently high. With the demand for higher-speed inter-chip communication, DFEs have become increasingly more important. In a DFE, in order to cancel the first post-tap ISI, each decision data bit has to be fed back within 1T (1UI) and the second post-tap feedback will also become a serious problem for the higherspeed communications. Though widely used half-rate clock DFEs with loopunrolled architectures (speculative feedback) extend the first post-tap feedback time limit to 2T for data sampling [1] (or 1.5T for edge sampling [2]), the

👥 作者与机构

Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki

NEC, Sagamihara, Japan