A 43.7mW 96GHz PLL in 65nm CMOS

📋 论文概要

该论文提出了一款在65nm CMOS工艺中实现的96GHz锁相环（PLL），旨在为W波段应用（如77GHz防撞系统、94GHz成像系统和100Gb/s以太网收发器）提供稳定的参考频率/时钟。通过设计，该PLL实现了低功耗（43.7mW）和高频操作，解决了毫米波频段频率合成中的功耗和性能挑战。

💡 主要创新点

• 采用65nm CMOS工艺实现了96GHz的高频PLL，突破了传统工艺在毫米波频段的限制。
• 通过优化电路架构和功耗管理，在96GHz下实现了43.7mW的低功耗，适合W波段应用。

🏷 关键词

📄 原文摘要

Advances in nanoscale CMOS technology have made it feasible to implement W-Band circuits in CMOS. Recently, CMOS implementation of high-frequency circuits for applications such as 77GHz anti-collision systems, 94GHz imaging systems, and 100Gb/s Ethernet transceivers has attracted a lot of attention. In high-speed wireless and wireline communication systems, PLLs are one of the key building blocks and are extensively used to generate a stable reference frequency/clock. In this paper, a 96GHz PLL, implemented in 65nm CMOS, is presented that targets W-band applications. Figure 16.2.1 shows the block diagram of the PLL. It is composed of a VCO, a low-power divider chain with the division ratio of 256, a PFD[1], a charge pump (CP), and a 2nd-order loop filter (LF). In the VCO design, a symmetric inductor and a cross-coupled pair are adopted to achieve a high oscillation frequency and a low power consumption. For the divider chain, the four different

👥 作者与机构

Kun-Hung Tsai, Shen-Iuan Liu

National Taiwan University, Taipei, Taiwan