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该论文提出了一种在65nm CMOS工艺中实现的60GHz频段功率放大器，采用1V电源电压，实现了11.5dBm的饱和输出功率和11%的峰值功率附加效率（PAE），解决了深亚微米CMOS技术中低电源电压限制输出摆幅和饱和功率的问题。
output power in Fig. 22.4.3. The maximum saturated output power is 11.5dBm, with a peak PAE close to 11% at 9dBm output power. The measured small-signal gain is also slightly higher than given in Fig. 22.4.2 at 58GHz, as different equipment and calibration are used for the large-signal measurements of the same test sample. 2 Sub-1V supplies limit the output voltage swing and saturated output power of an amplifier integrated in deep-submicron CMOS technology. Aside from absolute output power, power-added efficiency (PAE), stability and gain are also important power-amplifier (PA) design considerations. High reverse isolation between output and input is necessary to mitigate the effects of antenna mismatch, limit unwanted interference between circuit blocks on-chip and
Wei L. Chan1, John R. Long1, Marco Spirito1, John J. Pekarik2, 1
Delft University of Technology, Delft, Netherlands IBM, Burlington, VT The measured gain and PAE at 58GHz are plotted versus the PA