A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management

📋 论文概要

该论文提出了一种在32nm高k金属栅CMOS工艺下实现的4.0 GHz 291Mb电压可缩放SRAM设计，集成了功率管理模块，解决了纳米尺度下SRAM在性能提升与漏电降低之间的平衡问题。

💡 主要创新点

• 采用电压可缩放技术，允许SRAM在宽电压范围内动态调整性能与功耗
• 集成片上功率管理单元，实现高效的电压调节和功耗优化
• 在32nm高k金属栅工艺中实现了4.0 GHz的高速操作和291Mb的大容量

🏷 关键词

📄 原文摘要

Y. Zhang, K. Zhang, M. Bohr Intel, Hillsboro, OR CMOS technology has followed Moore’s law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role in determining the scaling of SRAM operating voltage (VCC), frequency and leakage power. We develop a high-performance voltage-scalable SRAM design in 32nm logic CMOS featuring 2nd-generation high-κ metal-gate transistors and 4th-generation strained silicon [1]. With the continued transistor performance enhancement and extensive process-circuit co-optimization, the 32nm SRAM design is able to achieve 2× improvement in density and 15% faster access speed when compared to the 45nm design [2]

👥 作者与机构

Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei,