A Process–Variation-Tolerant Dual-Power-Supply SRAM with 0.179µm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver

📋 论文概要

这篇论文提出了一种在40nm CMOS工艺下采用双电源供电的SRAM，通过通道面积节省实现了0.179µm2的小单元面积（比趋势小10%）。为解决小通道面积单元的稳定性问题，采用了字线电平控制方案和自适应编程及动态阵列电源控制技术，提高了工作裕度。

💡 主要创新点

• 采用双电源供电的字线电平控制方案，通过自适应编程提高SRAM单元稳定性
• 动态阵列电源控制技术，增加SRAM工作裕度
• 通过通道面积节省实现比缩放趋势小10%的单元面积

🏷 关键词

📄 原文摘要

T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, T. Yabe Toshiba Semiconductor, Kawasaki, Japan A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM. Continued technology scaling causes device variability, which is one of the most important issues for SoC design. The issue is especially serious for highdensity SRAM because of the small device size and large capacity. Increasing

👥 作者与机构

O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida,