A 2ns-Read-Latency 4Mb Embedded Floating-Body Memory Macro in 45nm SOI Technology

📋 论文概要

本文提出了一种基于浮体Z-RAM®存储单元的4Mb嵌入式存储器宏，在45nm SOI工艺下实现了2ns的读取延迟，解决了传统嵌入式存储器密度与速度之间的矛盾。

💡 主要创新点

• 采用单晶体管浮体Z-RAM®单元替代传统6T SRAM单元，显著提高存储密度。
• 通过优化读取路径和时序控制，在45nm SOI工艺下实现了2ns的读取延迟，达到与SRAM相当的性能。

🏷 关键词

📄 原文摘要

Philippe Bauser1, Paul de Champs1, Hamid Daghighian1, David Fisch1, Philippe Graber1, Michel Bron1 Innovative Silicon, Lausanne, Switzerland, 2AMD, Fort Collins, CO 1 To meet advancing market demands, microprocessor embedded memory applications require denser and faster memory arrays with each process generation. Recent work presented an 18.5ns 128Mb DRAM with a floating body cell for conventional DRAM products [1] and a 4Mb memory macro using a memory cell built with two floating body transistors [2]. This paper presents a floating-body Z-RAM® memory cell [3] to fabricate a high-density low-latency and high-bandwidth 4Mb memory macro building block, targeted at the requirements of microprocessor caches. It uses a single transistor (1T), unlike traditional 1T1C DRAM [4], or six transistor 6T-SRAM memory cells [5]. The macro supports a 2ns read latency, a 4ns write latency, and a high-speed

👥 作者与机构

Anant Singh1, Michael Ciraula2, Don Weiss2, John Wuu2,