Wireless DC Voltage Transmission Using InductiveCoupling Channelfor Highly-Parallel Wafer-Level Testing

📋 论文概要

本文提出一种基于电感耦合的无线直流电压传输通道，用于实现高并行度的晶圆级测试，解决了传统探针卡因探针数量限制而无法同时测试大量芯片的问题，从而降低测试成本。

💡 主要创新点

• 利用电感耦合实现无线直流电压传输，避免物理探针接触，提高测试并行度。
• 设计专门的电感耦合通道架构，适用于晶圆级测试场景，支持多芯片同时供电与信号传输。

🏷 关键词

📄 原文摘要

increased each year; the test cost especially for low-price IC chips, for example, exceeds one-third of total chip cost. Furthermore, screening test on wafer to select good dies (KnownGood-Die) will become more significant to improve the yields of up-to-date packages such as Chip-on-Chip and 3D-LSI. Therefore, the cost reduction for screening test will be a key issue to maintain continuous LSI-performance scaling. Increasing the number of dies under test (DUT-chips) at a time by increasing the number of needles on the probe card is effective to reduce the test cost per chip. However, this is problematic because it is difficult to ensure that all needles on a probe card contact the pads on the DUT-chips. An effective way to avoid such

👥 作者与机构

Yoichi Yoshida1, Koichi Nose2, Yoshihiro Nakagawa2, Koichiro Noguchi2,

Yasuhiro Morita2, Masamoto Tago2, Tadahiro Kuroda1, Masayuki Mizuno2 1 Keio University, Kanagawa, Japan, 2NEC, Sagamihara, Japan The cost for screening test on wafer has continually