An Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM

📋 论文概要

本文提出一种基于电感耦合的3D集成技术，将90nm CMOS八核处理器和65nm CMOS 1MB SRAM堆叠集成，通过磁耦合实现无导线通信，解决了传统3D集成中垂直互连的高寄生和工艺复杂度问题。

💡 主要创新点

• 采用电感耦合代替物理引脚实现芯片间通信，降低寄生效应并提高能效
• 将处理器和SRAM分别减薄至50µm并采用面对面/背对背堆叠方式，实现紧凑3D封装
• 成功集成商用处理器和存储器，验证了电感耦合在3D系统中实际应用的可行性

🏷 关键词

📄 原文摘要

Yoshinori Kohama1, Kazutaka Kasuga1, Itaru Nonomura2, Makoto Saen3, Shigenobu Komatsu3, Kenichi Osada3, Naohiko Irie3, Toshihiro Hattori2, Atsushi Hasegawa2, Tadahiro Kuroda1 1 Keio University, Yohohama, Japan 2 Renesas Technology, Tokyo, Japan 3 Hitachi, Tokyo, Japan This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65nm CMOS 1MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different supply voltages are AC-coupled by inductive coupling that provides a 19.2Gb/s data link. Measured power and area efficiency of the link is 1pJ/b and 0.15mm2/Gbps, which is 1/30 and 1/3 in comparison with the conventional DDR2 interface respectively [1]. The

👥 作者与机构

Kiichi Niitsu1, Yasuhisa Shimazaki1,2, Yasufumi Sugimori1,